View L6569D013TR_1698370.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/13 l6569 l6569a june 2000 this is preliminary information on a new product now in development. details are subject to change without notice. n high voltage rail up to 600v n bcd off line technology n internal bootstrap diode structure n 15.6v zener clamp on v s n driver current capability: - sink current = 270ma - source current = 170ma n very low start up current: 150 m a n under voltage lockout with hysteresis n programmable oscillator frequency n dead time 1.25 m s n dv/dt immunity up to 50v/ns n esd protection description the device is a high voltage half bridge driver with built in oscillator. the frequency of the oscillator can be programmed using external resistor and capaci- tor. the internal circuitry of the device allows it to be driven also by external logic signal. the output drivers are designed to drive external n- channel power mosfet and igbt. the internal log- ic assures a dead time [typ. 1.25 m s] to avoid cross- conduction of the power devices. two version are available: l6569 and l6569a. they differ in the low voltage gate driver start up sequence. minidip so8 ordering numbers: l6569 l6569d l6569a l6569ad high voltage half bridge driver with oscillator block diagram r f c f logic bias regulator comp comp level shifter buffer r f c f gnd high side driver low side driver hvg lvg out boot v s r hv c vs c boot h.v. load d94in058d charge pump source 18 7 6 5 4 3 2 v s v s
l6569 l6569a 2/13 absolute maximum ratings (*)the device has an internal zener clamp between gnd and vs (typical 15.6v).therefore the circuit should not be driven by a dc low im- pedance power source. note: esd immunity for pins 6, 7 and 8 is guaranteed up to 900 v (human body model) thermal data recommended operating conditions pin connection symbol parameter value unit i s (*) supply current 25 ma v cf oscillator resistor voltage 18 v v lvg low side switch gate output 14.6 v v out high side switch source output -1 to v boot - 18 v v hvg high side switch gate output -1 to v boot v v boot floating supply voltage 618 v v boot/out floating supply vs out voltage 18 v dv boot /dt vboot slew rate (repetitive) 50 v/ns dv out /dt vout slew rate (repetitive) 50 v/ns t stg storage temperature -40 to 150 c t j junction temperature -40 to 150 c t amb ambient temperature (operative) -40 to 125 c symbol parameter minidip so8 unit r th j-amb thermal resistance junction-ambient max 100 150 c/w symbol parameter min. max. unit v s supply voltage 10 v cl v v boot floating supply voltage - 500 v v out high side switch source output -1 v boot -v cl v f out oscillation frequency 200 khz v s r f c f gnd 1 3 2 4 lvg out hvg boot 8 7 6 5 d94in059
3/13 l6569 l6569a pin function electrical characteristcs (v s = 12v; v boot - v out = 12v; t j = 25c; unless otherwise specified.) n pin description 1 vs supply input voltage with internal clamp [typ. 15.6v] 2 rf oscillator timing resistor pin. a buffer set alternatively to v s and gnd can provide current to the external resistor rf connected between pin 2 and 3. alternatively, the signal on pin 2 can be used also to drive another ic (i.e. another l6569 to drive a full h-bridge) 3 cf oscillator timing capacitor pin. a capacitor connected between this pin and gnd fixes (together with r f ) the oscillating frequency alternatively an external logic signal can be applied to the pin to drive the ic. 4 gnd ground 5 lvg low side driver output. the output stage can deliver 170ma source and 270ma sink [typ.values]. 6 out upper driver floating reference 7 hvg high side driver output. the output stage can deliver 170ma source and 270ma sink [typ.values]. 8 boot bootstrap voltage supply. it is the upper driver floating supply. the bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named bootstrap driver (a patented structure). this structure can replace the external bootstrap diode. symbol pin parameter test condition min. typ. max. unit v suvp 1 vs turn on threshold 8.3 9 9.7 v v suvn vs turn off threshold 7.3 8 8.7 v v suvh vs hysteresis 0.7 1 1.3 v v cl vs clamping voltage i s = 5ma 14.6 15.6 16.6 v i su start up current v s < v suvn 150 250 m a i q quiescent current v s > v suvp 500 700 m a i bootlk 8 leakage current boot pin vs gnd v boot = 580v 5 m a i outlk 6 leakage current out pin vs gnd v out = 562v 5 m a i hvg so 7 high side driver source current v hvg = 6v 110 175 ma i hvg si high side driver sink current v hvg = 6v 190 275 ma i lvg so 5 low side driver source current v lvg = 6v 110 175 ma i lvg s i low side driver sink current v lvg = 6v 190 275 ma
l6569 l6569a 4/13 oscillator frequency the frequency of the internal oscillator can be programmed using external resistor and capacitor. the nominal oscillator frequency can be calculated using the following equation: where r f and c f are the external resistor and capacitor. the device can be driven in "shut down" condition keeping the c f pin close to gnd, but some cares have to be taken: 1. when c f is to gnd the high side driver is off and the low side is on 2. the forced discharge of the oscillator capacitor c f must not be shorter than 1us: a simple way to do this is to limit the current discharge with a resistive path imposing r c f >1 m s (see fig.1) figure 1. v rfo n 2 rf high level output voltage i rf = 1ma v s -0.05 v s -0.2 v v rf off rf low level output voltage i rf = -1ma 50 200 mv v cfu 3 cf upper threshold 7.7 8 8.2 v v cfl cf lower threshold 3.80 4 4.3 v t d internal dead time 0.85 1.25 1.65 m s dc duty cycle, ratio between dead time + conduction time of high side and low side drivers 0.45 0.5 0.55 r on on resistance of boostrap ldmos 120 w v bc boostrap voltage before uvlo v s = 8.2 2.5 3.6 v i ave 1 average current from vs no load, fs = 60khz 1.2 1.5 ma f out 6 oscillation frequency r t = 12k; c t = 1nf 57 60 63 khz symbol pin parameter test condition min. typ. max. unit f osc 1 2r f c f in2 ---------------------------------------- - 1 1.3863 r f c f ------------------------------------------ == r f c f gnd m 1 2 3 4 8 7 6 5 fault si g nal r electrical characteristcs (continued)
5/13 l6569 l6569a bootstrap function the l6569 has an internal bootstrap structure that enables the user to avoid the external diode needed, in sim- ilar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the upper external mosfet. the operation is achieved with an unique structure (patented) that uses a high voltage lateral dmos driven by an internal charge pump (see block diagram) and synchronized, with a 50 nsec delay, with the low side gate driver (lvg pin), actually working as a synchronous rectifier . the charging path for the bootstrap capacitor is closed via the lower external mosfet that is driven on (i.e. lvg high) for a time interval: t c = r f c f in2 ? 1.1 r f c f starting from the time the supply voltage v s has reached the turn on voltage (v suvp = 9 v typical value). after time t 1 (see waveform diagram) the ldmos that charges the bootstrap capacitor, is on with a r on =120 w (typical value). in the l6569a a different start up procedure is followed (see waveform diagram). the lower external mosfet is drive off until v s has reached the turn on threshold (v suvpp ), then again the t c time interval starts as above. being the ldmos used to implement the bootstrap operation a "bi-directional" switch the current flowing into the boot pin (pin 8) can lead an undue stress to the ldmos itself if a zero voltage switching opera- tions is not ensured, and then an high voltage is applied to the boot pin. this condition can occur, for example, when the load is removed and an high resistive value is placed in series with the gate of the external power mos. to help the user to secure his design a safe operating area for the bootstrap ldmos is provided (fig. 7). let's consider the steps that should be taken. 1) calculate the turn on delay ( td ) of your lower power mos: 2) calculate the fall time ( tf ) of your lower power mos: where: r g = external gate resistor r id = 50 w , typical equivalent output resistance of the driving buffer (when sourcing current) v th , c iss and q gd are power mos parameters v s = low voltage supply. 3) sketch the vboot waveform (using log-log scales) starting from the drain voltage of the lower power mos (remember to add the vs, your low voltage supply, value) on the bootstrap ldmos soa . on fig. 8 an example is given where: v s = low voltage supply v hv = high voltage supply rail the v boot voltage swing must fall below the curve identified by the actual operating frequency of your applica- tion. t d r g r id + () c iss 1 1 v th v s ---------- - C -------------------- ln = t f r g r id + v s v th C ------------------------ q gd =
l6569 l6569a 6/13 demo board to allow an easy evaluation of the device, a p.c. board dedicated to lamp ballast application has been de- signed. fig.11 shows the electrical schematic of a typical ballast application, while the pc and component layout is giv- en in fig12. this application has been designed to work with both the 110+/-20%v and the 220 +/- 20%v mains by means of a voltage doubler configuration at the bulk capacitor. the ballast inductance and the operating fre- quency are especially designed for a 18 w sylvania de-luxe t/e type bulb. the ptc for preheat at the start up and the two back to back synchronization diodes, makes this application easy to implement and safe in opera- tion. part value r1 15ohm 1w r2, r3 22 ohm r4 27k r5 100k 1/2w r6 47ohm r7, r9 180k r8 120k 1/2w d1 18v zener d2, d3 byw100-100 d4,d5,d6,d7 1n4007 d8 1n4148 c1 560pf 50v c2, c5 47 m f 250v c3 4.7 m f 25v c4 100nf 50v c6 100nf 250v c7-c8 8.2nf 630v c9 470pf 630v rv1 ptc 150ohm q1, q2 std2nb50-1 l1 2.4mh
7/13 l6569 l6569a figure 2. waveforms (l6569) figure 3. waveforms (l6569a) v s 4.6v(typ) t =ron*c boot t1 t c v s v boot -v out v cf lvg d95in250b v suvp v s 4.6v(typ) t =ron*c boot t1 t c v s v boot -v out v cf lvg d95in251b v suvp
l6569 l6569a 8/13 figure 4. typical dead time vs. temperature dependency figure 5. typical frequency vs temperature dependency figure 6. typical and theoretical oscillator frequency vs resistor value figure 7. v boot pin soa for different operating frequency @ t j = 125c figure 8. v boot pin soa @ t j = 125c figure 9. typical rise and fall times vs. load capacitance -50 0 50 100 150 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 temperature [c] dead time [ m sec] d96in378a -50 -25 0 25 50 75 100 125 55 56 57 58 59 60 61 62 63 64 65 temperature [ c ] frequency [khz] d96in379a 56789101520304050 20 30 50 60 70 80 90 100 150 resistor value (kohm) f (khz) theoretical c=1nf c=560pf c=330pf d96in380 20 50 100 200 500 1,000 2,000 5,000 10,000 10 20 30 50 100 200 300 500 time ( ns ) , from lvg transition hi g h vboot (v) 20khz 50khz 150khz 110khz 70khz d96in381 20 50 100 200 500 1,000 2,000 5,000 10,000 10 20 30 50 100 200 300 500 time ( ns ) , from lvg transition hi g h vboot (v) actual opertating frequency v hv +v s d96in416 t d t f v s vboot for both hi g h and low side buffers @25?c tamb 0123456 0 50 100 150 200 250 300 c [nf] time [nsec] tr tf d96in417
9/13 l6569 l6569a figure 10. quiescent current vs. supply voltage. figure 11. cfl demoboard 110/220v inputs. 02468101214v s (v) 10 10 2 10 3 10 4 iq ( m a) d96in418 l1=2.4mh l1=2.4mh core th lcc e2006-b4 ref also vogh 575 0409200 2.4mh c7-c8=ps8n2j h3 630-2a th d7 d4 d5 d6 r1 15 1w c2 47 m f 250v r8 120k 1/2w r5 100k c5 47 m f 250v c3 4.7 m f 25v d8 1n4148 d1 zpd 18v r4 27k 1/4w c1 560pf 50v 220v n 110v r6 47 1/4w r2 22 1/4w 1/4w r3 22 1/4w c4100nf 50v d2 d3 byw100-100 c9 470pf 630v q1 std2nb50-1 q2 std2nb50-1 r7 180k 1/4w c6 100nf 250v c8 8.2nf 630v c7 8.2nf 630v cfl lamp sylvania delux t/e 18w r9 180k 1/4w l6569 d96in419b v s rf cf gnd lvg out hvg boot 4 x 1n4006 1/2w byw100-100 r10 10k rv1 ptc 150 350v
l6569 l6569a 10/13 figure 12. pc board and components layout. component side copper side
11/13 l6569 l6569a dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.020 c1 45 (typ.) d (1) 4.8 5.0 0.189 0.197 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f (1) 3.8 4.0 0.15 0.157 l 0.4 1.27 0.016 0.050 m 0.6 0.024 s8 (max.) (1) d and f do not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch). so8 outline and mechanical data
l6569 l6569a 12/13 minidip dim. mm inch min. typ. max. min. typ. max. a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060 outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 13/13 l6569 l6569a

▲Up To Search▲

Price & Availability of L6569D013TR

	To Download L6569D013TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .